In recent years there has been significant effort focused on integrating perovskite-type insulators (most notably Barium Strontium Titanate, or BST) into high-density DRAM memory structures. These materials are crystalline dielectric materials, which exhibit large dielectric responses (relative to conventional amorphous dielectric materials, such as SiO2) due to ionic displacements within their crystal lattice. Similarly, there have been renewed efforts to develop viable high-density, non-volatile memory circuits based on ferroelectric dielectric materials. Ferroelectric materials are also crystalline dielectric materials and also possess the additional property of a permanent electric dipole moment whose orientation direction can be changed with an external electric field. From a fabrication standpoint, combining these crystalline dielectric materials with silicon processing poses serious difficulties. For example, forming the proper crystal structure (to obtain desired dielectric properties) requires high processing temperatures, which can have a detrimental effect on other parts of the circuit. Also, because these dielectric materials are crystalline, a film thereof has a grain structure and orientation that play a crucial role in determining device characteristics, such as leakage and polarization.
Recent work has shown that the grain size in crystalline dielectric films (in particular, much work has been done on BST) can be influenced somewhat by film deposition conditions. Upon crystallization to the high-dielectric phase, some films can become quite porous. Voids between grains in the dielectric can cause electrical shorts for sufficiently thin films. Problems associated with film grain size have become important as attempts are made to fabricate devices that are roughly the same size as the film granularity. These problems can be demonstrated with an example of a high density memory device.
Referring to FIG. 1, a high density memory device 10 includes a transistor 12 disposed below a capacitor 14. Transistor 12 and capacitor 14 are connected through a polycrystalline silicon (poly-Si) plug 16. The capacitor contains a crystalline dielectric material. FIG. 2 shows a difficulty in fabricating high density memory device 10. In order to obtain the proper crystal phase (with desirable properties) of the crystalline dielectric material, it is often necessary to subject the crystalline dielectric material to a high-temperature (>600° C.) anneal in oxygen. However, this process is detrimental to the rest of high-density memory device 10, because at high temperature, the oxygen diffuses down to and oxidizes poly-Si plug 16 it, converting it from a conductor to an insulator, thereby rendering high density memory device 10 inoperable.
Efforts have been made to develop a conducting barrier layer to place between a bottom electrode of capacitor 14 and poly-Si plug 16. The requirements for such a barrier are stringent, i.e., it must be electrically conducting, stop oxygen diffusion, and be non-reactive with oxygen at temperatures up to >600° C. These problems are major obstacles to the development high-density memory devices using crystalline dielectric materials.